The request of a miniaturization and high density fabrication of LSI has become much severer, and a sub 100-nm generation has come. On the other hand, the request of a low power consumption and high speed operation has been increased. It becomes difficult to satisfy those requests by using a conventional bulk substrate.
MISFET (Metal-Insulator-Semiconductor Field Effect Transistor) formed on an SOI substrate is expected as a ULSI element in the sub 100-nm generation, since junction capacitances in source and drain regions are small, a substrate bias effect is low and a sub-threshold characteristic is excellent, as compared with conventional MISFET formed on a bulk substrate.
The SOI-MISFET is grouped into two kinds of operation modes of a fully-depleted SOI-MISFET (hereafter, referred to as an FD-type SOI-MISFET) and a partially-depleted SOI-MISFET (hereafter, referred to as PD-SOI-MISFET). In the FD-type SOI-MISFET, the film thickness of a SOI layer is thinner than a maximum depletion layer (a body region is always in a depleted state), whereas in the PD-type SOI-MISFET, the film thickness of the SOI layer is thicker than a maximum depletion layer. In particular, the FD-type SOI-MISFET could be expected as the ULSI element having a low voltage operation and an excellent ultra high speed operation since a sharp sub-threshold characteristic can be obtained. In the FD-type SOI-MISFET in the sub 100 nm generation, the film thickness of a silicon layer on an SOI substrate is reduced to about 10 nm or less.
A method of manufacturing a conventional SOI-MISFET will be described below.
At first, a case that a shallow trench isolation (hereafter, referred to as STI) is applied to a typical MISFET on a bulk substrate will be described with reference to sectional views of FIGS. 1A to 2B (hereafter, referred to as a first conventional example). An SOI substrate is provided which has a silicon substrate 51, a buried oxide film 52 and a silicon film 53 (FIG. 1A). A pad oxide film 54 having the film thickness of about 5 nm and a stopper nitride film 55 of about 120 nm are sequentially deposited. Then, by using a photo-lithography and a reactive ion etching (hereafter, referred to as RIE) method, the stopper nitride film 55, the pad oxide film 54 and the silicon film 53 are patterned to an island shape, and element isolation trenches are formed (FIG. 1B). Subsequently, an STI embedded insulating film 57 is deposited, and a chemical mechanical polishing (hereafter, referred to as CMP) method is used to flatten the STI embedded insulating film 57 (FIG. 1C).
Next, the stopper nitride film 55 is removed by wet etching of hot phosphoric acid, and the pad oxide film 54 is removed by wet etching of fluoric acid, such that the silicon film 53 is exposed (FIG. 1D). At this time, the buried oxide film 52 in the lower portion of the silicon film 53 is over-etched 59. Then, a gate insulating film 60 is formed, and a polysilicon film 61 is deposited, and then is patterned to form a gate electrode (FIG. 2A). Subsequently, side wall insulating films 63, source and drain regions 64 and a silicide film 65 are formed, and an interlayer insulating film 66 is deposited. Then, contact holes are opened, and metal wirings 67 are formed. Thus, the MISFET is formed (FIG. 2B). FIG. 2C is a plan view showing the MISFET. FIGS. 1A to 2B are sectional views of the MISFET along a line A–A′ of FIG. 2C.
FIGS. 3A to 3D are sectional views showing a method of forming an element insulation region disclosed in Japanese Laid Open Patent Application (JP-A 2001-24202) (hereafter, referred to as a second conventional example). A gate insulating film 68 and a first polysilicon film 70 are deposited in this order on the surface of the silicon film of the SOI substrate in which the buried oxide film 52 and the silicon film 53 are laminated on a silicon substrate 51. Then, the first polysilicon film 70, the gate insulating film 68 and the silicon film 53 are patterned by using a same mask (FIG. 3A). Subsequently, an STI embedded insulating film 69 is deposited on the entire surface, and is flattened by using a CMP method (FIG. 3B).
Next, a second polysilicon film 71 is deposited on the entire surface, and a mask pattern 58 of photo resist is formed (FIG. 3C). By using this mask pattern 58, the second polysilicon film 71, the first polysilicon film 40 and the gate insulating film 68 are patterned by a RIE method. Here, the first polysilicon film 70 functions as a gate electrode 70a, and the second polysilicon film 71 functions as a gate electrode wiring line 71a through which gate electrodes of transistors adjacent to each other are connected. Subsequently, source and drain regions 64 are formed by ion implantation. Thus, the structure of FIG. 3D is obtained.
In the SOI-MISFET, it is known that the exposure of ends 72 of an element region causes a leak current to flow. However, according to this element insulation method, the side of the silicon film 53 on which the element is formed is covered with the STI embedded insulating film 69. Thus, the ends 72 of the element region are not exposed, and the leak current is suppressed (it should be noted that the location where the leak current is generated is the end existing in a direction perpendicular to FIG. 3D, but it is shown in FIG. 3D for the illustrative convenience).
A typical film thickness of a silicon film is about 10 nm in a higher density generation. However, if the STI structure is applied to the SOI-MISFET having such a thin silicon film, there are the following problems in the first conventional example. After the formation of the shape shown in FIG. 1C, the stopper nitride film 55 is removed by the wet etching method of the hot phosphoric acid, and the pad oxide film 54 is further removed by the wet etching method of HF. At this time, the STI embedded insulating film 57 is also etched by HF at the same time. Thus, as shown in FIG. 1D, the buried oxide film 52 under the silicon film 53 is over-etched (numeral 59 of FIG. 1D). In particular, if the silicon film 53 is thin (for example, in a case of 10 nm), when the pad oxide film 54 is etched, the entire STI embedded insulating film 57 on the side of the silicon film 53 is easily lost through the etching. Therefore, the over-etching 59 is extremely easily caused in the lower corner of the end of the silicon film 53.
Moreover, the gate insulating film 60 is formed in the state that the buried oxide film 52 at the lower corner of the end of the silicon film 53 is over-etched. Then, the polysilicon film 61 is deposited. Subsequently, when the polysilicon film 61 is patterned, a residual polysilicon film 62 is left in the over-etched portion 59 (FIG. 2A).
As shown in the plan view of FIG. 2C, the residual polysilicon film 62 is formed to surround an active region (an island region). This results in the connection between the residual polysilicon film 62 and the polysilicon film 61 on a B–B′ section. At this time, if two or more gate electrodes are arranged in parallel to each other, the gate electrodes are short-circuited to each other through the residual polysilicon film 62. In addition, a capacitance generated between the residual polysilicon film 62 and each of the source and drain regions 64 functions as a parasitic capacitance connected in parallel to the gate capacitance. This increases a load on the circuit to decrease the operation speed. Also, if the insulation characteristic of the gate insulating film 60 is deteriorated due to the damage caused by the ion implantation to form the source and drain regions 64, there may be a possibility that an electric short-circuit is caused between the gate electrode and the each of the source and drain regions 64 through the residual polysilicon film 62.
Also, if the formation of the over-etched portion 59 causes the element end to be exposed, a leak current easily flows in the end (numeral 72 of FIG. 3D) of the element region.
Moreover, in the first conventional example, the end of the element region is exposed so that the gate electrode is formed to cover the side of the element region. Therefore, the electric field applied to the silicon film from the gate electrode is increased. Thus, the reverse narrow channel effect becomes severe to decrease the threshold through the miniaturization.
In order to prevent the above-mentioned over-etching, it could be considered to strictly control the wet etching of the pad oxide film 54 by HF, although this control is very difficult actually. At this time, a step will be generated as shown in FIG. 4. This is because the film thickness of the pad oxide film 54 is very thinner than that of the STI embedded insulating film 57. Also, if the wet etching with HF is continued in order to remove this step, the above-mentioned over-etched portion would be generated.
Here, the problem when the step is generated will be described with reference to FIG. 5. In case of the existence of such a step, when the polysilicon film 61 is deposited (FIG. 5A) after the formation of the gate insulating film 60, and the gate electrode is formed by etching this polysilicon film 61 by the RIE method, non-etched polysilicon films 62 is remained in the step portions (FIG. 5B). This residual polysilicon film 62 acts as a cause of short circuit between the polysilicon films or between the gate electrode and each of the source and drain regions. Also, such a step deteriorates the shape of a resist pattern for a gate electrode in a lithography step.
Also, in the second conventional example, if a polishing operation is carried out by the CMP method in order to process as shown in FIG. 3B, the first polysilicon film 70 is polished deeper than the STI embedded insulating film 69, because a polishing rate of the polysilicon film is typically larger than a polishing rate of the oxide film. This results in the formation of a step (FIG. 6A). Moreover, the first polysilicon film 70 can not function as a stopper to the polishing operation in the CMP method. Therefore, if the polysilicon film is a thin film, there may be a possibility that the polysilicon film is perfectly lost (FIG. 6B).
By the way, a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-74538). The semiconductor device of this conventional example has a substrate having an insulating layer. A first conductive type semiconductor layer is formed on the insulating layer such that a part of the semiconductor layer functions as a channel region. A gate insulating film is formed on the channel region of the semiconductor layer, and a gate electrode is formed on the gate insulating layer. A second conductive type source and drain regions are respectively formed on both sides of the channel region within the semiconductor layer. A hole removing region is formed in a region within the semiconductor layer, and the hole removing region is adjacent to the channel region and at least one region of the source region and the drain region, and has a function of preventing the accumulation of a hole of a pair of a hole and an electron generated in the channel region.
Also, a SOI device is disclosed in Japanese Laid Open Patent Application (JP-A 2001-24202). The SOI device of this conventional example contains an SOI substrate constituted of a lamination structure of a base substrate, a buried oxide film and a semiconductor layer. An oxide film is formed so as to be in contact with the buried oxide film in a semiconductor portion of a field region so as to determine an active region. Each of gate electrode patterns has a gate oxide film formed only on the active region, and source and drain regions are formed within the active regions of the semiconductor layer on both sides of the gate electrode pattern. A gate electrode line is formed on the gate electrode pattern and the field region to connect the gate electrode patterns formed on the respective aligned active regions.
Also, a separation structure of a semiconductor device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei, 11-67895). The separation structure of the semiconductor device includes a semiconductor substrate having an active region and a field region. A buried insulating layer is formed in a predetermined depth within the active region of the semiconductor substrate, and a separation layer is formed in a position deeper than the buried insulating layer within the field region of the semiconductor substrate.